1. Field of the Invention
The present invention relates to a semiconductor device such as a memory cell transistor.
2. Description of the Background Art
FIG. 36 is a cross sectional view of transistors of an ordinary generic DRAM (Dynamic Random Access Memory) according to a prior art. A gate oxide film 102 is formed beneath a gate electrode and a thermal oxide film 107 is formed in places other than that, above a silicon substrate. Source/drain regions to which an impurity is introduced are placed so as to sandwich a channel region beneath a gate conductive layer. The above described semiconductor device of FIG. 36 is a type wherein a thermal oxide film (lower layer oxide film) 107 is formed on a side of the gate conductive layer and on the silicon substrate. The portion of this thermal oxide film 107 on the side of the gate conductive layer is, in some cases, particularly referred to as sidewall internal layer oxide film.
Next, in reference to FIGS. 37 to 43, a manufacturing method for a transistor shown in FIG. 36 is described. First, an element isolation region is formed in a semiconductor substrate by using a method of filling in a thermal oxide film and an oxide film, or the like. A portion other than the element isolation region becomes an active region. Implantations for a well, a channel, and the like, of the transistor to the active region are carried out. After that a silicon oxide film 102, which becomes a gate oxide film, is formed and a conductive film 103, which becomes a wire, is layered on top of the oxide film. An insulating film 104 for the protection of the wire is formed on top of the conductive film (FIG. 37).
Next, a photoresist mask 105 of a desired gate wire pattern is applied (FIG. 38) according to a photomechanical process. Next, insulating film 104 is formed into a desired pattern (FIG. 39) by using dry etching, primarily of the oxide film, by means of an RIE (reactive ion etching) method, or the like. Dry etching, primarily of the polymetal, is carried out by means of an RIE method, or the like, by using insulating film 104 as a mask so as to form a gate wire form. Etching at this time is, in general, carried out under the condition of having a high etching selection ratio relative to silicon oxide film. Therefore, etching stops in the gate oxide film 102 (FIG. 40). Next, impurities such as P or As in the order of 1013 to 1014 atoms/cm2 are implanted into source/drain regions 106 of the transistor (FIG. 41).
Next, a thermal oxidation process is carried out so as to cover the sidewalls of the gate wire and the substrate with a thermal oxide film (layer oxide film) 107 (FIG. 42).
Next, a gate protective film 108 of an insulating film is deposited in order to protect a sidewall of the gate wire. An insulating film having a high etching selection ratio at the time of the dry etching of the oxide film by means of an RIE method, or the like, is used for this gate protective film 108. This is usually a nitride film or an oxy-nitride (SiNxOy) film that is deposited by means of a CVD (chemical vapor deposition) method. In either case, the film thickness is 10 nm to 100 nm (FIG. 43). Next, dry etching, of primarily the oxide film, is carried out on the entire surface by means of an RIE method, or the like, so that a sidewall 9 of a nitride film or an oxy-nitride film is formed.
When sidewalls of a nitride film or an oxy-nitride film are formed as shown in FIG. 43, stress given by these sidewalls becomes a problem. The stress acting on the semiconductor substrate increases the leak current of the transistor and causes the deterioration of the refreshing characteristics. In addition, the stress acting on the gate wires lowers the driving ability of the transistor.
In particular, in recent years miniaturization has progressed and high melting point metal films have come into use as wire materials in order to lower wire resistance. However, high melting point metal films have a high sensitivity to thermal oxidation processes and yield unfavorable results when a thermal oxidation process is carried out. Accordingly, in the case that a high melting point metal film is used as a conductive material for gate wires, a thermal oxidation process cannot be carried out. The semiconductor device shown in FIG. 44 is a semiconductor device of this type. Since a thermal oxidation process cannot be carried out, a sidewall external layer spacer 109 contacts a gate conductive layer 103. In addition, the oxide film positioned between the nitride film of the sidewall external layer spacer and the silicon substrate remains thin. As a result of this, stress acting on the semiconductor substrate and the gate wires becomes greater in comparison with the semiconductor device of the type wherein a lower layer oxide film is provided. Therefore, the driving ability and refreshing characteristics of the transistor are caused to deteriorate and a problem arises wherein the leak current increases.
An object of the present invention is to provide a semiconductor device having a structure in which stress acting on the semiconductor substrate or the gate wires is reduced, even in the case that a sidewall of a gate wire is formed of a nitride film, or the like.
A semiconductor device of the present invention is provided with: a gate conductive layer positioned on a silicon substrate; a stress mitigating film including a silicon film which covers a sidewall of said gate conductive layer and the silicon substrate beneath the gate conductive layer; and a sidewall external layer spacer covering the stress mitigating film and exposing an upper edge of the stress mitigating film in an upper portion of the sidewall of the gate conductive layer and a side edge of a bottom portion of the stress mitigating film in a lower portion of the gate conductive layer, wherein the stress mitigating film has silicon oxide films positioned in an area ranging inwardly from the upper edge and from the side edge so as to sandwich the silicon film from both ends.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.